1. Technical Field
The present invention relates to data processing systems, and more particularly to apparatus for controlling data flow between an input/output bus and a local memory of an input/output processor.
2. Background Art
The above identified copending patent application Ser. No. 921,313 addresses the basic I/O problem of how to couple two different bus types and provide for data flow between these two buses. One of the busses is an I/O bus. On the I/O bus different devices having a spectrum of data rates generated by different peripherals must be handled. Some devices have the added problem of quiet periods followed by very busy periods with sharp transitions between the two periods.
In the past the I/O bus data transfer problem has been solved by using buffers for the data. For example, in the Capowski, et al. U.S. Pat. No. 3,699,530 granted to IBM on Oct. 17, 1972, multiple dedicated buffers are provided for each channel to ensure that all channels have an individual receptacle for receiving data which cannot be made unavailable due to transfers by other channels. Prior resolution of requests from channels control the use of the bus from the channel independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned dedicated buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. In this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses.
This approach has the advantage that it does smooth out input/output transfers, but at the expense of requiring dedicated resources which are expensive. In modern very large integrated (VLSI) technology, chip space is at a premium and pin connections are limited. It therefore becomes important to reduce the amount of buffering provided on the chip while still maintaining data throughput efficiency. This is best achieved by providing shared rather than dedicated resources.
It is therefore an object of the present invention to provide an input/output sequencer to handle transfers between an I/O bus and a shared register file.